1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a stacked semiconductor device in which a plurality of semiconductor chips are stacked.
2. Description of the Related Art
In a stacked semiconductor device in which a plurality of semiconductor chips are stacked, electric power is supplied to the respective semiconductor chips from power source terminals formed on a semiconductor chip located on one side of the stacked semiconductor device in a stacking direction of the semiconductor chips (i.e., the uppermost semiconductor chip or the lowermost semiconductor chip). For the power supply, through electrodes are formed so as to extend through semiconductor substrates of those semiconductor chips.
For example, the through electrodes formed in the respective semiconductor chips are connected in series to each other in the stacking direction of the semiconductor chips. Ends of those through electrodes are connected to the power source terminals to produce power supply lines. Thus, a pair of power supply lines is produced. A circuit element (or a functional circuit) is formed on each of the semiconductor chips. The circuit elements formed on the respective semiconductor chips are connected in parallel to each other between those power supply lines. Thus, electric power can be supplied to the circuit elements formed on the semiconductor chips.
With the above configuration, however, a voltage drop is caused by the electric resistance of the through electrodes. As a circuit element of a semiconductor chip is located farther away from the power source terminals, a power source voltage supplied to that circuit element decreases. The electric resistance of through electrodes tends to increase because the diameter of through electrodes is reduced according to miniaturization of a semiconductor device and progress of technology. Therefore, such a drop of the power source voltage is not negligible.
In order to prevent a drop of a power source voltage as described above, a related semiconductor device uses a loop structure in which power source lines formed on a semiconductor chip located on another side of the stacked semiconductor device in the stacking direction of semiconductor chips are connected to the corresponding power source terminals by bonding wires. See, e.g., JP-A 2007-194444 (Patent Literature 1).
Furthermore, in another related semiconductor device, internal components of semiconductor chips are connected in series between a power source voltage and a ground voltage by using through electrodes. An intermediate voltage that corresponds to a stacked location of a semiconductor chip is supplied as a high potential power source to the respective internal components. See, e.g., JP-A 2008-159736 (Patent Literature 2).
The semiconductor device disclosed in Patent Literature 1 requires a space for arranging the bonding wires. Therefore, it is difficult to reduce the size and thickness of the semiconductor device.
Furthermore, the semiconductor device disclosed in Patent Literature 2 requires power source terminals and through electrodes for supplying the intermediate voltage in proportion to the number of the stacked semiconductor chips. Therefore, the number of power source terminals and through electrodes increases as the number of the stacked semiconductor chips increases. Thus, the configuration of the semiconductor device becomes complicated.